ARM is a family of  for  based on a (RISC)  developed by British company .

A RISC-based computer design approach means ARM processors require significantly fewer transistors than typical processors in average computers. This approach reduces costs, heat and power use. These are desirable traits for light, portable, battery-powered devices—including , ,  and notepad computers, and other . A simpler design facilitates more efficient  CPUs and higher core counts at lower cost, providing higher processing power and improved energy efficiency for  and .

ARM Holdings develops the instruction set and architecture for ARM-based products, but does not manufacture products. The company periodically releases updates to its cores. Current cores from ARM Holdings support a   and 32-bit arithmetic; the recently introduced ARMv8-A architecture adds support for a  address space and 64-bit arithmetic. Instructions for ARM Holdings' cores have 32-bit-wide fixed-length instructions, but later versions of the architecture also support a variable-length instruction set that provides both 32-bit and 16-bit-wide instructions for improved code density. Some cores can also provide hardware execution of .

ARM Holdings  the chip designs and the ARM instruction set architectures to third-parties, who design their own products that implement one of those architectures—including  (SoC) that incorporate memory, interfaces, radios, etc. Currently, the widely used Cortex cores, older "classic" cores, and specialized  cores variants are available for each of these to include or exclude optional capabilities. Companies that produce ARM products include , , , , , and . Apple first implemented the ARMv8-A architecture in the  chip in the .

In 2005, about 98% of all mobile phones sold used at least one ARM processor. The low power consumption of ARM processors has made them very popular: 37 billion ARM processors have been produced as of 2013, up from 10 billion in 2008. The ARM architecture (32-bit) is the most widely used architecture in mobile devices, and most popular 32-bit one in embedded systems.

According to ARM Holdings, in 2010 alone, producers of chips based on ARM architectures reported shipments of 6.1 billion , representing 95% of , 35% of  and  and 10% of . It is the most widely used 32-bit instruction set architecture in terms of quantity produced.

History[]

The British computer manufacturer  first developed ARM in the 1980s to use in its personal computers. Its first ARM-based products were coprocessor modules for the  series of computers. After the successful BBC Micro computer, Acorn Computers considered how to move on from the relatively simple  processor to address business markets like the one that was soon dominated by the , launched in 1981. The  (ABC) plan required that a number of second processors be made to work with the BBC Micro platform, but processors such as the  and  were considered unsuitable, and the 6502 was not powerful enough for a graphics based user interface.

After testing all available processors and finding them lacking, Acorn decided it needed a new architecture. Inspired by white papers on the  project, Acorn considered designing its own processor. A visit to the  in Phoenix, where the 6502 was being updated by what was effectively a single-person company, showed Acorn engineers  and  they did not need massive resources and state-of-the-art  facilities.

Wilson developed the instruction set, writing a simulation of the processor in  that ran on a BBC Micro with a second 6502 processor. This convinced Acorn engineers they were on the right track. Wilson approached Acorn's CEO, , and requested more resources. Once he had approval, he assembled a small team to implement Wilson's model in hardware.

Acorn RISC Machine: ARM2[]

The official Acorn RISC Machine project started in October 1983. They chose  as the silicon partner, as they were a source of ROMs and custom chips for Acorn. Wilson and Furber led the design. They implemented it with a similar efficiency ethos as the 6502. A key design goal was achieving low-latency input/output (interrupt) handling like the 6502. The 6502's memory access architecture had let developers produce fast machines without costly  hardware.

VLSI produced the first ARM silicon on 26 April 1985. It worked the first time, and was known as ARM1 by April 1985. The first production systems named ARM2 were available the following year.

The first practical ARM application was as a second processor for the BBC Micro, where it helped developed simulation software to finish development of the support chips (VIDC, IOC, MEMC), and sped up the  used in ARM2 development. Wilson subsequently rewrote BBC Basic in ARM assembly language. The in-depth knowledge gained from designing the instruction set enabled the code to be very dense, making ARM BBC Basic an extremely good test for any ARM emulator. The original aim of a principally ARM-based computer was achieved in 1987 with the release of the . In 1992, Acorn once more won the  for the ARM.

The ARM2 featured a 32-bit ,  address space and 27 32-bit . 8 bits from the  register were available for other purposes; the top 6 bits (available because of the 26-bit address space), served as status flags, and the bottom 2 bits (available because the program counter was always ), were used for setting modes. The address bus was extended to 32 bits in the ARM6, but program code still had to lie within the first 64  of memory in 26-bit compatibility mode, due to the reserved bits for the status flags. The ARM2 had a  of just 30,000, compared to Motorola's six-year-older 68000 model with 68,000. Much of this simplicity came from the lack of  (which represents about one-quarter to one-third of the 68000) and from (like most CPUs of the day) not including any . This simplicity enabled low power consumption, yet better performance than the . A successor, ARM3, was produced with a 4  cache, which further improved performance.

Apple, DEC, Intel, Marvell: ARM6, StrongARM, XScale[]

In the late 1980s  and  started working with Acorn on newer versions of the ARM core. In 1990, Acorn spun off the design team into a new company named Acorn RISC Machines Ltd., which became ARM Ltd when its parent company, ARM Holdings plc, floated on the  and  in 1998.

The new Apple-ARM work would eventually evolve into the ARM6, first released in early 1992. Apple used the ARM6-based ARM610 as the basis for their Apple Newton PDA. In 1994, Acorn used the ARM610 as the main  (CPU) in their  computers.  licensed the ARM6 architecture and produced the StrongARM. At 233 , this CPU drew only one watt (newer versions draw far less). This work was later passed to Intel as a part of a lawsuit settlement, and Intel took the opportunity to supplement their  line with the StrongARM. Intel later developed its own high performance implementation named XScale, which it has since sold to . Transistor count of the ARM core remained essentially the same size throughout these changes; ARM2 had 30,000 transistors, while ARM6 grew only to 35,000.^[]

Licensing[]

Core license[]

ARM Holdings' primary business is selling , which licensees use to create  (MCUs) and  based on those cores. The  combines the ARM core with other parts to produce a complete CPU, typically one that can be built in existing  at low cost and still deliver substantial performance. The most successful implementation has been the TDMI with hundreds of millions sold. Atmel has been a precursor design center in the ARM7TDMI-based embedded system.

The ARM architectures used in smartphones, PDAs and other  range from ARMv5, used in low-end devices, through ARMv6, to ARMv7 in current high-end devices. ARMv7 includes a hardware  (FPU), with improved speed compared to software-based floating-point.

In 2009, some manufacturers introduced netbooks based on ARM architecture CPUs, in direct competition with netbooks based on . According to analyst firm IHS iSuppli, by 2015, ARM ICs may be in 23% of all laptops.

ARM Holdings offers a variety of licensing terms, varying in cost and deliverables. ARM Holdings provides to all licensees an integratable hardware description of the ARM core as well as complete software development toolset (, ,) and the right to sell manufactured  containing the ARM CPU.

SoC packages integrating ARM's core designs include Nvidia Tegra's first three generations, CSR plc's Quatro family, ST-Ericsson's Nova and NovaThor, Silicon Labs's Precision32 MCU, Texas Instruments's OMAP products, Samsung's Hummingbird and  products, Apple's , , and, and Freescale's i.MX.

Fabless licensees, who wish to integrate an ARM core into their own chip design, are usually only interested in acquiring a ready-to-manufacture verified . For these customers, ARM Holdings delivers a  description of the chosen ARM core, along with an abstracted simulation model and test programs to aid design integration and verification. More ambitious customers, including integrated device manufacturers (IDM) and foundry operators, choose to acquire the processor IP in   () form. With the synthesizable RTL, the customer has the ability to perform architectural level optimisations and extensions. This allows the designer to achieve exotic design goals not otherwise possible with an unmodified netlist (, very low power consumption, instruction set extensions, etc.). While ARM Holdings does not grant the licensee the right to resell the ARM architecture itself, licensees may freely sell manufactured product such as chip devices, evaluation boards, complete systems.   can be a special case; not only are they allowed to sell finished silicon containing ARM cores, they generally hold the right to re-manufacture ARM cores for other customers.

ARM Holdings prices its IP based on perceived value. Lower performing ARM cores typically have lower licence costs than higher performing cores. In implementation terms, a synthesizable core costs more than a hard macro (blackbox) core. Complicating price matters, a merchant foundry that holds an ARM licence, such as Samsung or Fujitsu, can offer fab customers reduced licensing costs. In exchange for acquiring the ARM core through the foundry's in-house design services, the customer can reduce or eliminate payment of ARM's upfront licence fee.

Compared to dedicated semiconductor foundries (such as  and ) without in-house design services, Fujitsu/Samsung charge two- to three-times(2~3) more per manufactured .^[] For low to mid volume applications, a design service foundry offers lower overall pricing (through subsidisation of the licence fee). For high volume mass-produced parts, the long term cost reduction achievable through lower wafer pricing reduces the impact of ARM's NRE (Non-Recurring Engineering) costs, making the dedicated foundry a better choice.

Architectural licence[]

Companies can also obtain an ARM architectural licence for designing their own CPU cores using the ARM instruction sets. These cores must comply fully with the ARM architecture.

Cores[]

A list of vendors who implement ARM cores in their design (application specific standard products (ASSP), microprocessor and microcontrollers) is provided by ARM Holdings.

Example applications of ARM cores[]

ARM cores are used in a number of products, particularly  and . Some computing examples are the , Apple's iPad and . Others include Apple's iPhone smartphone and iPod portable media player, digital camera,  handheld game console and  turn-by-turn navigation system.

In 2005, ARM Holdings took part in the development of Manchester University's computer, , which used ARM cores to simulate the human brain.

ARM chips are also used in , , ,  and other , because they are very small, inexpensive and consume very little power.

32-bit architecture[]

The 32-bit ARM architecture, such as ARMv7-A, is the most widely used architecture in mobile devices.

From 1995, the  has been the primary source of documentation on the ARM processor architecture and instruction set, distinguishing interfaces that all ARM processors are required to support (such as instruction semantics) from implementation details that may vary. The architecture has evolved over time, and version 7 of the architecture, ARMv7, that defines the architecture for the first of the Cortex series of cores, defines three architecture "profiles": 

• A-profile, the "Application" profile:  series
• R-profile, the "Real-time" profile:  series
• M-profile, the "Microcontroller" profile:  series

Although the architecture profiles were first defined for ARMv7, ARM subsequently defined the ARMv6-M architecture (used by the Cortex //) as a subset of the ARMv7-M profile with fewer instructions.

CPU modes[]

Except in the M-profile, the 32-bit ARM architecture specifies several CPU modes, depending on the implemented architecture features. At any moment in time, the CPU can be in only one mode, but it can switch modes due to external events (interrupts) or programmatically.

User mode

The only non-privileged mode.

FIQ mode

A privileged mode that is entered whenever the processor accepts an FIQ interrupt.

IRQ mode

A privileged mode that is entered whenever the processor accepts an IRQ interrupt.

Supervisor (svc) mode

A privileged mode entered whenever the CPU is reset or when an SVC instruction is executed.

Abort mode

A privileged mode that is entered whenever a prefetch abort or data abort exception occurs.

Undefined mode

A privileged mode that is entered whenever an undefined instruction exception occurs.

System mode (ARMv4 and above)

The only privileged mode that is not entered by an exception. It can only be entered by executing an instruction that explicitly writes to the mode bits of the CPSR.

Monitor mode (ARMv6 and ARMv7 Security Extensions, ARMv8 EL3)

A monitor mode is introduced to support TrustZone extension in ARM cores.

Hyp mode (ARMv7 Virtualization Extensions, ARMv8 EL2)

A hypervisor mode that supports virtualization of the non-secure operation of the CPU.

Instruction set[]

The original ARM implementation was hardwired without , like the much simpler   processor used in prior Acorn microcomputers.

The 32-bit ARM architecture (and the 64-bit architecture for the most part) includes the following RISC features:

• .
• No support for  in the original version of the architecture. ARMv6 and later, except some microcontroller versions, support unaligned accesses for half-word and single-word load/store instructions with some limitations, such as no guaranteed .
• Uniform 16× 32-bit  (including the Program Counter, Stack Pointer and the Link Register).
• Fixed instruction width of 32 bits to ease decoding and , at the cost of decreased . Later, the  added 16-bit instructions and increased code density.
• Mostly single clock-cycle execution.

To compensate for the simpler design, compared with processors like the Intel 80286 and , some additional design features were used:

• Conditional execution of most instructions reduces branch overhead and compensates for the lack of a .
• Arithmetic instructions alter  only when desired.
• 32-bit  can be used without performance penalty with most arithmetic instructions and address calculations.
• Powerful indexed .
• A  supports fast leaf function calls.
• A simple, but fast, 2-priority-level  subsystem has switched register banks.

Arithmetic instructions[]

The ARM supports add, subtract, and multiply instructions. The integer divide instructions are only implemented by ARM cores based on the following ARM architectures:

• ARMv7-M and ARMv7E-M architectures always include divide instructions.
• ARMv7-R architecture always includes divide instructions in the Thumb instruction set, but optionally in its 32-bit instruction set.
• ARMv7-A architecture optionally includes the divide instructions. The instructions might not be implemented, or implemented only in the Thumb instruction set, or implemented in both the Thumb and ARM instructions sets, or implemented if the Virtualization Extensions are included.

Registers[]

Registers R0 through R7 are the same across all CPU modes; they are never banked.

R13 and R14 are banked across all privileged CPU modes except system mode. That is, each mode that can be entered because of an exception has its own R13 and R14. These registers generally contain the stack pointer and the return address from function calls, respectively.

Aliases:

• R13 is also referred to as SP, the Stack Pointer.
• R14 is also referred to as LR, the Link Register.
• R15 is also referred to as PC, the Program Counter.

CPSR has the following 32 bits.

• M (bits 0–4) is the processor mode bits.
• T (bit 5) is the Thumb state bit.
• F (bit 6) is the FIQ disable bit.
• I (bit 7) is the IRQ disable bit.
• A (bit 8) is the imprecise data abort disable bit.
• E (bit 9) is the data endianness bit.
• IT (bits 10–15 and 25–26) is the if-then state bits.
• GE (bits 16–19) is the greater-than-or-equal-to bits.
• DNM (bits 20–23) is the do not modify bits.
• J (bit 24) is the Java state bit.
• Q (bit 27) is the sticky overflow bit.
• V (bit 28) is the overflow bit.
• C (bit 29) is the carry/borrow/extend bit.
• Z (bit 30) is the zero bit.
• N (bit 31) is the negative/less than bit.

Conditional execution[]

Almost every ARM instruction has a conditional execution feature called , which is implemented with a 4-bit condition code selector (the predicate). To allow for unconditional execution, one of the four-bit codes causes the instruction to be always executed. Most other CPU architectures only have condition codes on branch instructions.

Though the predicate takes up 4 of the 32 bits in an instruction code, and thus cuts down significantly on the encoding bits available for displacements in memory access instructions, it avoids branch instructions when generating code for small . Apart from eliminating the branch instructions themselves, this preserves the fetch/decode/execute pipeline at the cost of only one cycle per skipped instruction.

The standard example of conditional execution is the subtraction-based :

In the , the loop is:

while (i != j)    {
              if (i > j)       {
                  i -= j;       }       else  /* i < j (since i != j in while condition) */       {
                  j -= i;       }    }

In ARM , the loop is:

loop:   CMP  Ri, Rj         ; set condition "NE" if (i != j),                            ;               "GT" if (i > j),                            ;            or "LT" if (i < j)        SUBGT  Ri, Ri, Rj   ; if "GT" (Greater Than), i = i-j;        SUBLT  Rj, Rj, Ri   ; if "LT" (Less Than), j = j-i;        BNE  loop           ; if "NE" (Not Equal), then loop

which avoids the branches around the then and else clauses. If Ri and Rj are equal then neither of the SUB instructions will be executed, eliminating the need for a conditional branch to implement the while check at the top of the loop, for example had SUBLE (less than or equal) been used.

One of the ways that Thumb code provides a more dense encoding is to remove the four bit selector from non-branch instructions.

Other features[]

Another feature of the  is the ability to fold shifts and rotates into the "data processing" (arithmetic, logical, and register-register move) instructions, so that, for example, the C statement

a += (j << 2);

could be rendered as a single-word, single-cycle instruction:

ADD  Ra, Ra, Rj, LSL #2

This results in the typical ARM program being denser than expected with fewer memory accesses; thus the pipeline is used more efficiently.

The ARM processor also has features rarely seen in other RISC architectures, such as -relative addressing (indeed, on the 32-bit ARM the  is one of its 16 registers) and pre- and post-increment addressing modes.

The ARM instruction set has increased over time. Some early ARM processors (before ARM7TDMI), for example, have no instruction to store a two-byte quantity.

Pipelines and other implementation issues[]

The ARM7 and earlier implementations have a three-stage ; the stages being fetch, decode and execute. Higher-performance designs, such as the ARM9, have deeper pipelines: Cortex-A8 has thirteen stages. Additional implementation changes for higher performance include a faster adder and more extensive branch prediction logic. The difference between the ARM7DI and ARM7DMI cores, for example, was an improved multiplier; hence the added "M".

Coprocessors[]

The ARM architecture provides a non-intrusive way of extending the instruction set using "coprocessors" that can be addressed using MCR, MRC, MRRC, MCRR, and similar instructions. The coprocessor space is divided logically into 16 coprocessors with numbers from 0 to 15, coprocessor 15 (cp15) being reserved for some typical control functions like managing the caches and  operation on processors that have one.

In ARM-based machines, peripheral devices are usually attached to the processor by mapping their physical registers into ARM memory space, into the coprocessor space, or by connecting to another device (a bus) that in turn attaches to the processor. Coprocessor accesses have lower latency, so some peripherals—for example an XScale interrupt controller—are accessible in both ways: through memory and through coprocessors.

In other cases, chip designers only integrate hardware using the coprocessor mechanism. For example, an image processing engine might be a small ARM7TDMI core combined with a coprocessor that has specialised operations to support a specific set of HDTV transcoding primitives.

Debugging[]

All modern ARM processors include hardware debugging facilities, allowing software debuggers to perform operations such as halting, stepping, and breakpointing of code starting from reset. These facilities are built using  support, though some newer cores optionally support ARM's own two-wire "SWD" protocol. In ARM7TDMI cores, the "D" represented JTAG debug support, and the "I" represented presence of an "EmbeddedICE" debug module. For ARM7 and ARM9 core generations, EmbeddedICE over JTAG was a de facto debug standard, though not architecturally guaranteed.

The ARMv7 architecture defines basic debug facilities at an architectural level. These include breakpoints, watchpoints and instruction execution in a "Debug Mode"; similar facilities were also available with EmbeddedICE. Both "halt mode" and "monitor" mode debugging are supported. The actual transport mechanism used to access the debug facilities is not architecturally specified, but implementations generally include JTAG support.

There is a separate ARM "CoreSight" debug architecture, which is not architecturally required by ARMv7 processors.

Tools[]

The ARM architecture is supported by a set of development tools such as Emprog ThunderBench for ARM. Such tools allow development engineers to program the ARM architecture device using a high level language like C.

DSP enhancement instructions[]

To improve the ARM architecture for  and multimedia applications, DSP instructions were added to the set. These are signified by an "E" in the name of the ARMv5TE and ARMv5TEJ architectures. E-variants also imply T,D,M and I.

The new instructions are common in  architectures. They include variations on signed , saturated add and subtract, and count leading zeros.

SIMD extensions for multimedia[]

Introduced in ARMv6 architecture.

Jazelle[]

Jazelle DBX (Direct Bytecode eXecution) is a technique that allows Java Bytecode to be executed directly in the ARM architecture as a third execution state (and instruction set) alongside the existing ARM and Thumb-mode. Support for this state is signified by the "J" in the ARMv5TEJ architecture, and in ARM9EJ-S and ARM7EJ-S core names. Support for this state is required starting in ARMv6 (except for the ARMv7-M profile), though newer cores only include a trivial implementation that provides no hardware acceleration.

Thumb[]

To improve compiled code-density, processors since the ARM7TDMI (released in 1994) have featured Thumb instruction set, which have their own state. (The "T" in "TDMI" indicates the Thumb feature.) When in this state, the processor executes the Thumb instruction set, a compact 16-bit encoding for a subset of the ARM instruction set. Most of the Thumb instructions are directly mapped to normal ARM instructions. The space-saving comes from making some of the instruction operands implicit and limiting the number of possibilities compared to the ARM instructions executed in the ARM instruction set state.

In Thumb, the 16-bit opcodes have less functionality. For example, only branches can be conditional, and many opcodes are restricted to accessing only half of all of the CPU's general-purpose registers. The shorter opcodes give improved code density overall, even though some operations require extra instructions. In situations where the memory port or bus width is constrained to less than 32 bits, the shorter Thumb opcodes allow increased performance compared with 32-bit ARM code, as less program code may need to be loaded into the processor over the constrained memory bandwidth.

Embedded hardware, such as the , typically have a small amount of RAM accessible with a full 32-bit datapath; the majority is accessed via a 16-bit or narrower secondary datapath. In this situation, it usually makes sense to compile Thumb code and hand-optimise a few of the most CPU-intensive sections using full 32-bit ARM instructions, placing these wider instructions into the 32-bit bus accessible memory.

The first processor with a Thumb  was the ARM7TDMI. All ARM9 and later families, including XScale, have included a Thumb instruction decoder.

Thumb-2[]

Thumb-2 technology was introduced in the ARM1156 core, announced in 2003. Thumb-2 extends the limited 16-bit instruction set of Thumb with additional 32-bit instructions to give the instruction set more breadth, thus producing a variable-length instruction set. A stated aim for Thumb-2 was to achieve code density similar to Thumb with performance similar to the ARM instruction set on 32-bit memory. In ARMv7 this goal can be said to have been met.^[]

Thumb-2 extends the Thumb instruction set with bit-field manipulation, table branches and conditional execution. At the same time, the ARM instruction set was extended to maintain equivalent functionality in both instruction sets. A new "Unified Assembly Language" (UAL) supports generation of either Thumb or ARM instructions from the same source code; versions of Thumb seen on ARMv7 processors are essentially as capable as ARM code (including the ability to write interrupt handlers). This requires a bit of care, and use of a new "IT" (if-then) instruction, which permits up to four successive instructions to execute based on a tested condition, or on its inverse. When compiling into ARM code this is ignored, but when compiling into Thumb it generates an actual instruction. For example:

; if (r0 == r1)CMP r0, r1ITE EQ        ; ARM: no code ... Thumb: IT instruction; then r0 = r2;MOVEQ r0, r2  ; ARM: conditional; Thumb: condition via ITE 'T' (then); else r0 = r3;MOVNE r0, r3  ; ARM: conditional; Thumb: condition via ITE 'E' (else); recall that the Thumb MOV instruction has no bits to encode "EQ" or "NE"

All ARMv7 chips support the Thumb instruction set. All chips in the Cortex-A series, Cortex-R series, and ARM11 series support both "ARM instruction set state" and "Thumb instruction set state", while chips in the  series support only the Thumb instruction set.

Thumb Execution Environment (ThumbEE)[]

ThumbEE (erroneously called Thumb-2EE in some ARM documentation), marketed as  (Runtime Compilation Target), was announced in 2005, first appearing in the Cortex-A8 processor. ThumbEE is a fourth Instruction set state, making small changes to the Thumb-2 extended Thumb instruction set. These changes make the instruction set particularly suited to code generated at runtime (e.g. by ) in managed Execution Environments. ThumbEE is a target for languages such as , , , and , and allows  to output smaller compiled code without impacting performance. 

New features provided by ThumbEE include automatic null pointer checks on every load and store instruction, an instruction to perform an array bounds check, and special instructions that call a handler. In addition, because it utilises Thumb-2 technology, ThumbEE provides access to registers r8-r15 (where the Jazelle/DBX Java VM state is held). Handlers are small sections of frequently called code, commonly used to implement high level languages, such as allocating memory for a new object. These changes come from repurposing a handful of opcodes, and knowing the core is in the new ThumbEE Instruction set state.

On 23 November 2011, ARM Holdings deprecated any use of the ThumbEE instruction set, and ARMv8 removes support for ThumbEE.

Floating-point (VFP)[]

VFP (Vector Floating Point) technology is an FPU coprocessor extension to the ARM architecture. It provides low-cost  and  floating-point computation fully compliant with the . VFP provides floating-point computation suitable for a wide spectrum of applications such as PDAs, smartphones, voice compression and decompression, three-dimensional graphics and digital audio, printers, set-top boxes, and automotive applications. The VFP architecture was intended to support execution of short "vector mode" instructions but these operated on each vector element sequentially and thus did not offer the performance of true  (SIMD) vector parallelism. This vector mode was therefore removed shortly after its introduction, to be replaced with the much more powerful NEON Advanced SIMD unit.

Some devices such as the ARM Cortex-A8 have a cut-down VFPLite module instead of a full VFP module, and require roughly ten times more clock cycles per float operation. Other floating-point and/or SIMD coprocessors found in ARM-based processors include , FPE, . They provide some of the same functionality as VFP but are not -compatible with it.

VFPv1

Obsolete.

VFPv2

An optional extension to the ARM instruction set in the ARMv5TE, ARMv5TEJ and ARMv6 architectures.

VFPv3 or VFPv3-D32

Implemented on earlier ARMv7 processors (Cortex-A8 and A9) and is backwards compatible with VFPv2, except that it cannot trap floating-point exceptions. VFPv3 has 32x 64-bit FPU registers as standard, adds VCVT instructions to convert between scalar, float and double, adds immediate mode to VMOV such that constants can be loaded into FPU registers.

VFPv3-D16

As above, but it has only 16 64-bit FPU registers.

VFPv3-F16

Uncommon; it supports  .

VFPv4 or VFPv4-D32

Is implemented on later ARMv7 processors (Cortex-A12 and A15). VFPv4 has 32x 64-bit FPU registers as standard, adds both half-precision extensions and   instructions to the features of VFPv3.

VFPv4-D16

As above, but it has only 16x 64-bit FPU registers. Implemented on Cortex-A5 and A7 processors.

In  Linux and derivatives armhf (ARM hard float) refers to the ARMv7 architecture including the additional VFP3-D16 floating-point hardware extension (and Thumb-2) above. Software packages and cross-compiler tools use the armhf vs. arm/armel suffixes to differentiate.

Advanced SIMD (NEON)[]

The Advanced SIMD extension (aka NEON or "MPE" Media Processing Engine) is a combined 64- and  SIMD instruction set that provides standardized acceleration for media and signal processing applications. NEON is included in all Cortex-A8 devices but is optional in Cortex-A9 devices. NEON can execute MP3 audio decoding on CPUs running at 10 MHz and can run the   (AMR) speech  at no more than 13 MHz. It features a comprehensive instruction set, separate register files and independent execution hardware. NEON supports 8-, 16-, 32- and 64-bit integer and single-precision (32-bit) floating-point data and SIMD operations for handling audio and video processing as well as graphics and gaming processing. In NEON, the SIMD supports up to 16 operations at the same time. The NEON hardware shares the same floating-point registers as used in VFP. Devices such as the ARM Cortex-A8 and Cortex-A9 support 128-bit vectors but will execute with 64 bits at a time, whereas newer Cortex-A15 devices can execute 128 bits at a time.

 is ARM's first open source project (from its inception). The Ne10 library is a set of common, useful functions written in both NEON and C (for compatibility). The library was created to allow developers to use NEON optimizations without learning NEON but it also serves as a set of highly optimized NEON intrinsic and assembly code examples for common DSP, arithmetic and image processing routines. The code is available on .  

Security extensions (TrustZone)[]

The Security Extensions, marketed as TrustZone Technology, is in ARMv6KZ and later application profile architectures. It provides a low cost alternative to adding an additional dedicated security core to an SoC, by providing two virtual processors backed by hardware based access control. This lets the application core switch between two states, referred to as worlds (to reduce confusion with other names for capability domains), in order to prevent information from leaking from the more trusted world to the less trusted world. This world switch is generally orthogonal to all other capabilities of the processor, thus each world can operate independently of the other while using the same core. Memory and peripherals are then made aware of the operating world of the core and may use this to provide access control to secrets and code on the device.

Typical applications of TrustZone Technology are to run a rich operating system in the less trusted world, and smaller security-specialized code in the more trusted world (named TrustZone Software, a TrustZone optimised version of the Trusted Foundations Software developed by ), allowing much tighter  for controlling the use of media on ARM-based devices, and preventing any unapproved use of the device. Trusted Foundations Software was acquired by Gemalto. Giesecke & Devrient developed a rival implementation named Mobicore. In April 2012 ARM Gemalto and Giesecke & Devrient combined their TrustZone portfolios into a joint venture Trustonic. Open Virtualization is an open source implementation of the trusted world architecture for TrustZone. 

In practice, since the specific implementation details of TrustZone are proprietary and have not been publicly disclosed for review, it is unclear what level of assurance is provided for a given threat model.^[]

No-execute page protection[]

As of ARMv6, the ARM architecture supports , which is referred to as XN, for eXecute Never.

ARMv8-R[]

The ARMv8-R subarchitecture announced after the ARMv8-A shares some features except that it is not 64-bit.

64/32-bit architecture[]

ARMv8-A[]

Announced in October 2011, ARMv8-A (often called ARMv8 although not all variants are 64-bit such as ARMv8-R) represents a fundamental change to the ARM architecture. It adds a 64-bit architecture, named "AArch64", and a new "A64" instruction set. AArch64 provides  compatibility with ARMv7-A ISA, the 32-bit architecture, therein referred to as "AArch32" and the old 32-bit instruction set, now named "A32". The Thumb instruction sets are referred to as "T32" and have no 64-bit counterpart. ARMv8-A allows 32-bit applications to be executed in a 64-bit OS, and a 32-bit OS to be under the control of a 64-bit . ARM announced their Cortex-A53 and Cortex-A57 cores on 30 October 2012.

To both AArch32 and AArch64, ARMv8-A makes VFPv3/v4 and advanced SIMD (NEON) standard. It also adds cryptography instructions supporting  and /56.

AArch64 features[]

• New instruction set, A64
  • Has 31 general-purpose 64-bit registers.
  • Has separate dedicated SP and PC.
  • Instructions are still 32 bits long and mostly the same as A32 (with LDM/STM instructions and most conditional execution dropped).
    • Has paired loads/stores (in place of LDM/STM).
  • Most instructions can take 32-bit or 64-bit arguments.
  • Addresses assumed to be 64-bit.
• Advanced SIMD (NEON) enhanced
  • Has 32× 128-bit registers (up from 16), also accessible via VFPv4.
  • Supports double-precision floating point.
  • Fully IEEE 754 compliant
  • AES encrypt/decrypt and SHA-1/SHA-2 hashing instructions also use these registers.
• A new exception system
  • Fewer banked registers and modes.
• Memory translation from 48-bit virtual addresses based on the existing LPAE, which was designed to be easily extended to 64-bit.

Operating system support[]

32-bit operating systems[]

Historical operating systems

The first ARM-based personal computer, the Acorn Archimedes, ran an interim operating system called  , which evolved into  , used on later ARM-based systems from Acorn and other vendors. Some Acorn machines also had a   port called  .

Embedded operating systems

The ARM architecture is supported by a large number of   and  , including  ,  , ,  ,  ,  ,  ,  ,  ,  ,

  ,  ,  ,  , ,  ,  ,  ,  ,   and RISC OS.

Mobile device operating systems

The ARM architecture is the primary hardware environment for most mobile device operating systems such as iOS,  ,  ,  ,  ,  / ,  ,  ,  ,  ,   and  .

Desktop operating systems

The ARM architecture is supported by RISC OS and multiple   operating systems including   and various   such as   and  .

64-bit operating systems[]

Mobile device operating systems

 on the 64-bit   SOC has ARMv8-A application support.

Desktop operating systems

Patches to the   adding ARMv8-A support have been posted for review by Catalin Marinas of ARM Ltd. The patches have been included in kernel version 3.7 in late 2012.

 ARMv8-A is supported by some  .

See also[]

• , ARM's heterogeneous computing architecture
•  certification program

• , an open-source ARM-compatible processor core
• , an asynchronous implementation of the ARM architecture

• , a 32-register architecture based heavily on a 32-bit ARM.

This list provides an overview of the properties of  microprocessor cores.

This is a sub-article to .

This is a list of -based microprocessor cores by  and 3rd parties, sorted by generation release and name. ARM provides a summary of the numerous vendors who implement ARM cores in their design.  also provides a somewhat newer summary of vendors of ARM based processors. ARM further provides a chart displaying an overview of the ARM processor lineup with performance and functionality versus capabilities for the more recent ARM core families.

ARM cores[]

Designed by ARM[]

Designed by third parties[]

These cores implement the ARM instruction set, and were developed independently by companies with an architectural license from ARM.

The ARM Cortex-A8 is a processor core designed by  implementing the  () .

Compared to the  core, the Cortex-A8 is a dual-issue  design, achieving roughly twice the . The Cortex-A8 was the first Cortex design to be adopted on a large scale for use in consumer devices.

Key features of the Cortex-A8 core are:

• Frequency from 600 MHz to 1 GHz and above
•  dual-issue microarchitecture
•   instruction set extension 
• VFPv3 Floating Point Unit
•  instruction set encoding
•  (Also known as ThumbEE instruction set)
• Advanced branch prediction unit with >95% accuracy
• Integrated level 2 Cache (0–4 MiB)
• 2.0 /MHz

Chips[]

Several  (SoC) have implemented the Cortex-A8 core, including:

•  i.MX51 
•  RK2918, RK2906 
•  CX92755 

ARM Cortex-A9 MPCore

The ARM Cortex-A5 is a processor core designed by  implementing the  .

Overview[]

It is intended to replace the  and  cores for use in low-end devices. Compared to those older cores, the Cortex-A5 offers the advanced features of the ARM v7 architecture over the v4/v5 (ARM9) and v6 (ARM11) architectures e.g VFPv4 and NEON advanced SIMD. It also allows devices to run current software, which is increasingly focusing on ARM v7 and dropping support for earlier architectures.

Key features of the Cortex-A5 core are:

• ,  microarchitecture with an 8 stage 
•   instruction set extension (optional)
• VFPv4  (optional)
•  instruction set encoding
• 1.57  / MHz

Chips[]

Several  (SoC) have implemented the Cortex-A5 core, including:

•  
•  
•  SC8810 (single core A5 1ghz +  GPU)
•  ATM7029 (gs702a) is a quad-core Cortex-A5 configuration
• 2013  APUs will include a Cortex-A5 as a security co-processor

The ARM Cortex-A7 MPCore is a  designed by  implementing the  .

Overview[]

It has two target applications; firstly as a smaller, faster, and more power-efficient successor to the . The other use is in the architecture, combining one or more A7 cores with one or more  cores into a . To do this it is fully feature-compatible with the A15.

Key features of the Cortex-A7 core are:

• ,  microarchitecture with an 8 stage 
•   instruction set extension
• VFPv4 Floating Point Unit
•  instruction set encoding
• Hardware virtualization
• Large Page Address Extensions (LPAE)
• Integrated level 2 Cache (0-1 MB)
• 1.9  / MHz

Chips[]

Several  (SoC) have implemented the Cortex-A7 core, including:

•  (dual core A7 + -400 MP2 GPU)
•  (quad core A7 +  GPU)
•  BCM23550-Quad-core HSPA+ Multimedia Processor 
•  K3V3, big.LITTLE architecture with dual-core Cortex-A7 and dual-core Cortex-A15. Use ARM  GPU.
•  PXA1088 (quad core A7) 
•  MT6589 (quad core A7 +   GPU)
•   MSM8212 and MSM8612, MSM8226 and MSM8626 (quad core A7 +  305 GPU)
•   5 Octa (5410), big.LITTLE architecture with quad-core Cortex-A7 and quad-core Cortex-A15. Use   GPU.
•   5 Octa (5420), big.LITTLE architecture with quad-core Cortex-A7 and quad-core Cortex-A15. Use   GPU.

The ARM Cortex-A12 is a 32-bit multicore processor that has been designed to be the successor to the . It provides up to 4  cores, each implementing the   architecture.

Overview[]

ARM claims that the Cortex-A12 core is 40 percent more powerful than the  core. New features not found in the Cortex-A9 include hardware virtualization and 40-bit Large Physical Address Extensions (LPAE) addressing. The CPU can also be used in a big.LITTLE solution together with the Cortex-A7 processor.

Key features of the Cortex-A12 core are:

•    execution  giving 3.00 /MHz/core.
•   instruction set extension.
• High performance VFPv4 floating point unit.
•  instruction set encoding reduces the size of programs with little impact on performance.
•  security extensions.
• L2 cache controller (0-8 MB).
• Multi-core processing.
• 40-bit Large Physical Address Extensions (LPAE) addressing up to 1  of RAM.
•  support.

The ARM Cortex-A15 MPCore is a multicore  processor providing an   pipeline ARM v7  running at up to 2.5 .

Overview[]

ARM has claimed that the Cortex A15 core is 40 percent more powerful than the  core with the same number of cores at the same speed. The first A15 designs came out in the autumn of 2011, but products based on the chip did not reach the market until 2012.

Key features of the Cortex-A15 core are:

• 40-bit Large Physical Address Extensions (LPAE) addressing up to 1  of . As per the  , still only 32-bit address space is available per process.
• 15 stage integer/17–25 stage floating point pipeline, with   3-way execution pipeline
• 4 cores per cluster, up to 2 clusters per chip with CoreLink 400 (an AMBA-4 coherent interconnect). ARM provides specifications but the licencees individually design ARM chips, and AMBA-4 scales beyond 2 clusters.
• DSP and   extensions onboard (per core)
•  Floating Point Unit onboard (per core)
•  support
•  instruction set encoding reduces the size of programs with little impact on performance.
•  security extensions
•  for  compilation
• Program Trace Macrocell and CoreSight Design Kit for unobtrusive tracing of instruction execution
• 32 KB data + 32 KB instruction L1 cache per core
• Integrated low-latency level-2 cache controller, up to 4 MB per cluster

Chips[]

First implementation came from Samsung in 2012 with the Exynos 5 Dual, which shipped in October 2012 with the Samsung  Series 3 (ARM version), followed in November by the .

Implementations of other manufacturers are expected to hit market in 2013.

Press announcements of forthcoming implementations:

•  SoC
•  K3V3
•  
•   5 Dual
•   A9600 ( @ 2.5 GHz over 20k DMIPS)
•   SoCs

Other licensees, such as , are expected to produce an A15 based design at some point.

Systems on a chip[]

ARM big.LITTLE is a  architecture developed by  coupling (relatively) slower, low-power processor cores with (relatively) more powerful and power-hungry ones. The intention being to create a multi-core processor that can adjust better to dynamic computing needs and use less power than clock scaling alone. In October 2011, big.LITTLE was announced along with the , which was designed to be architecturally compatible with the. In October 2012 ARM announced the  and  () cores, which are also compatible with each other to allow their use in a big.LITTLE chip.

Cluster migration[]

There are three ways for the different processor cores to be arranged in a big.LITTLE design, depending on the scheduler implemented in the .The clustered model approach is the first and simplest implementation. With this approach the operating system scheduler can only see one of the two processor clusters, when the load on one cluster hits a certain point, the system transitions to the other cluster. All relevant data is passed through the common L2 cache, the first core cluster is powered off and the other one is activated. A Cache Coherent Interconnect (CCI) is used. This model has been implemented in the  5 Octa (5410)

In-kernel switcher (CPU migration)[]

CPU migration via the in-kernel switcher (IKS) involves pairing up a 'big' core with a 'LITTLE' core, with possibly many identical pairs in one chip. Each pair operates as one virtual core, and only one real core is (fully) powered up and running at a time. The 'big' core is used when demand is high, the 'LITTLE' core when demand is low. When demand on the virtual core changes (between high and low), the incoming core is powered up, running state is transferred, the outgoing is shut down, and processing continues on the new core. Switching is done via the cpufreq framework. A complete big.LITTLE IKS implementation is expected in Linux 3.11 or 3.12. big.LITTLE IKS is an improvement of Cluster Migration, the main difference is that each pair is visible to the scheduler.

The more complex arrangement involves a non-symmetric grouping of 'big' and 'LITTLE' cores. A single chip could have one or two 'big' cores and many more 'LITTLE' cores, or vice-versa. Nvidia created something similar to this with the low-power 'companion core' in their  SoC.

Heterogeneous multi-processing (global task scheduling)[]

The most powerful use model of big.LITTLE is heterogeneous multi-processing (MP), which enables the use of all physical cores at the same time. Threads with high priority or computational intensity can in this case be allocated to the 'big' cores while threads with less priority or less computational intensity, such as background tasks, can be performed by the 'LITTLE' cores. Upstream big.LITTLE GTS patches are expected to be fully incorporated into the mainline Linux kernel in a few quarters. This model has been implemented in the  5 Octa (5420)

Scheduling[]

The paired arrangement allows for switching to be done transparently to the operating system using the existing dynamic voltage and frequency switching (DVFS) facility. The existing DVFS support in the kernel (e.g. cpufreq in Linux) will simply see a list of frequencies/voltages and will switch between them as it sees fit, just like it does on existing hardware. However, the low-end slots will activate the 'LITTLE' core and the high-end slots will activate the 'big' core.

Alternatively, all cores may be exposed to the kernel scheduler, which will decide where each process/thread is executed. This will be required for the non-paired arrangement but could possibly also be used on paired cores. It poses unique problems for the kernel scheduler, which, at least with modern commodity hardware, has been able to assume all cores in a SMP system are equal.

Advantages of global task scheduling[]

• Finer-grained control of workloads that are migrated between cores. Because the scheduler is directly migrating tasks between cores, kernel overhead is reduced and power savings can be correspondingly increased.
• Implementation in the scheduler also makes switching decisions faster than in the cpufreq framework implemented in IKS.
• The ability to easily support non-symmetrical SoCs (e.g. with 2 Cortex-A15 cores and 4 Cortex-A7 cores).
• The ability to use all cores simultaneously to provide improved peak performance throughput of the SoC compared to IKS.

Implementations[]